1. Field of the Invention
The present invention relates to differential amplification of a semiconductor memory device. More particularly, it relates to a semiconductor memory device that amplifies memory data by comparing between readout-data and a reference value of a reference cell.
2. Description of Related Art
In a semiconductor memory device such as flash memory or the like, storing of data is determined by current drivability of non-volatile transistors provided with a memory cell array arranged in a matrix form. That is, data “1”/“0” correspond to difference such as that a non-volatile transistor allows current “to flow”/“not to flow”, or a non-volatile transistor allows “even more current”/“even less current” to flow, respectively, and the like.
Data stored in a non-volatile semiconductor memory device is sensed in such a manner that a memory cell is selected from a memory cell array arranged in a matrix form, and large-small relation is detected between two kinds of current values, namely, current that flows to ground voltage VSS from a digit line connected to the selected memory cell through the memory cell and reference current that flows to the ground voltage VSS from a reference digit line through a reference cell. In this situation, a current path between a memory cell and the ground voltage VSS differs from position by position of memory cells. Accordingly, different values of wiring resistance are applied to respective current paths as source resistance of respective non-volatile transistors for memory cells. Since source resistance works to restrict current drivability of a non-volatile transistor, current characteristics of memory cells are determined by difference of source resistance value.
Conventionally, there has been devised structure to resolve the above-described problem. For example, as shown in FIG. 18, Japanese Laid-open Patent Publication No. 4-67500 discloses a reference section 1000 that comprises: reference cells RC100, RC101, RC102, and RC103 each of which is connected to a line having the same value of resistance in comparison with that of wiring resistance of the current path between a memory cell and the ground voltage VSS; and decode circuits 300, 301, 302, and 303 which are controlled by column decode signals Y100, Y101, Y102, and Y103, respectively so as to select a reference cell positioned in a column address column of which is same as column of a selected memory cell. In the reference section 1000, a reference cell positioned in a column address column of which is same as column of a selected memory cell is selected and a wiring resistance to the ground voltage VSS of the selected memory cell and that of the reference cell are same. Accordingly, there is obtained reference current a value of which depends on a selected memory cell so that margin of readout operation can be uniform regardless any memory cells.
However, in the memory cell region of the conventional reference section 1000, there are required reference cells as many as memory cells arranged in a line. Such structure arises a problem such that as memory volume of a semiconductor memory device is increased, the number of reference cells must be increased. There will be listed problems of such structured reference cells in detail.
Redundancy structure may be provided for malfunction of memory cells. However, due to limitation of chip area in a semiconductor memory device, it is generally difficult to provide redundancy structure for reference cells in the device. Therefore, as the number of reference cells increases, rate of malfunction of the reference cells becomes higher. This lowers yield of non-defective, which is problematic. In case redundancy structure for reference cells is provided, circuit scale of a reference section becomes large. This makes chip size larger, which is problematic.
Although wiring resistances of non-volatile transistors, applied as source resistance, are balanced, the number of reference cells is increased. As a result, characteristic variation among the reference cells or between reference cells and memory cells becomes large and margin of readout operation in a manner of current comparison decreases. Aspects as such are problematic to a reference section.
In outgoing inspections, program operation must be conducted for each reference cell so as to adjust threshold voltage of each reference cell. The more reference cells are provided, the longer time for adjustment of threshold voltage and time for inspection are required, which is problematic.
Furthermore, circuit scale of a decode circuit must be made larger so as to select many reference cells. Additionally, the number of column decode signals to be sent to the decode circuit as control signal increases. As a region for the decode circuit and a wiring region for the column decode signal become large, chip size becomes larger naturally, which is problematic.
Furthermore, flash memories or the like have various operation modes such as erase verification (ERV, hereinafter), program verification (PGMV, hereinafter), readout operation (READ, hereinafter), and the like. Reference cells different in threshold voltage value are required for each operation mode. Since a set of reference cells as many as the number of addresses arranged in a column of memory cell array is required for each operation mode, a large number of cells are required as total number of reference cells. In addition to an area for a decode circuit and wirings of column decode signal, a large area is required for cells, which makes chip size large. What is more, characteristic variation among reference cells becomes large, whereby outgoing inspection time becomes significantly long. Those aspects are problematic.